家电科技 ›› 2025, Vol. 0 ›› Issue (zk): 138-142.doi: 10.19784/j.cnki.issn1672-0172.2025.99.029

• 第一部分 优秀论文 • 上一篇    下一篇

基于参数化分析与协同仿真的空调PCB抗EFT设计方法研究

吕继方1,2,3, 何振华2,3, 王晓莹2,3, 魏铁成2,3, 张宇翔2,3, 崔吉林2,3   

  1. 1.大规模个性化定制系统与技术全国重点实验室 山东青岛 266100;
    2.青岛海尔空调器有限总公司 山东青岛 266100;
    3.数字家庭网络国家工程研究中心 山东青岛 266100
  • 发布日期:2025-12-30
  • 通讯作者: 何振华,E-mail:hezhenhua@haier.com。
  • 作者简介:吕继方,博士学位,高级工程师。研究方向:家用电器、智能装备产品EMC 仿真、整改、硬件电路设计及控制等。
  • 基金资助:
    山东省博士后创新项目(SDCX-ZG-202400204)

Research on EFT immunity design methodology for air conditioning PCBs based on parametric analysis and co-simulation

Lyu Jifang1,2,3, He Zhenhua2,3, Wang Xiaoying2,3, Wei Tiecheng2,3, Zhang Yuxiang2,3, Cui Jilin2,3   

  1. 1. Laboratory of Massive Personalized Customization System and Technology Qingdao 266100;
    2. Qingdao Haier Air Conditioner Gen. Co., Ltd. Qingdao 266100;
    3. National Engineering Research Center of Digital Home Networking Qingdao 266100
  • Published:2025-12-30

摘要: 家用空调系统电路板的PCB布线布局质量对其在复杂电磁环境中的抗干扰性能具有决定性影响,现有设计方法因电磁耦合路径的复杂性,难以可靠预测EFT/B抗扰性能。基于此提出了一种基于关键参数分析与协同仿真的PCB布局优化方法。通过建立EFT耦合路径与布局参数的定量映射模型,解决传统设计中耦合路径黑盒化问题;利用ANSYS工具集构建“协同仿真-参数量化-设计优化”闭环流程,实现从故障根因定位到优化效果量化的全数字化验证;最终形成以“最小化关键回路电感与有害耦合”为核心的可工程化设计方案。实验测试表明,该方案可显著提升EFT抗扰性,降低主板平均改版次数并提高测试一次通过率,推动家电行业EMC质量管控向“事前预防”数字化转型。

关键词: EFT/B, PCB布局优化, 联合仿真, 参数化分析, 质量改进

Abstract: The quality of PCB routing and layout in household air conditioning systems is decisive for their anti-interference performance in complex electromagnetic environments. Existing design methodologies struggle to reliably predict immunity against Electrical Fast Transient/Burst (EFT/B) disturbances due to the intricacy of electromagnetic coupling paths. To address this challenge, a PCB layout optimization method based on critical parameter analysis and co-simulation is proposed. This research establishes a quantitative mapping model between EFT coupling paths and layout parameters, resolving the opaque nature of coupling mechanisms in traditional design approaches. A closed-loop workflow integrating co-simulation, parameter quantification, and design optimization is constructed using the ANSYS toolset, enabling comprehensive digital verification from root-cause fault identification to optimization effectiveness quantification. Ultimately, an engineering-ready design scheme centering on minimizing critical loop inductance and harmful coupling is developed. Experimental results demonstrate that this approach significantly enhances EFT immunity, reduces the average number of board revisions, and improves first-pass yield in compliance testing. This methodology facilitates the digital transformation of EMC quality management in the household appliance industry toward a proactive prevention paradigm.

Key words: EFT/B, PCB Layout optimization, Co-Simulation, Parametric analysis, Reliability enhancement

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